An efficient synaptic architecture for artificial neural networks
- 2017
- NVMTS 2017
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44 results for Yusuf Leblebici
Improved deep neural network hardware-Accelerators based on non-volatile-memory: The local gains technique
- Irem Boybat
- Carmelo Di Nolfo
- et al.
- 2017
- ICRC 2017
Feature learning using synaptic competition in a dynamically-sized neuromorphic architecture
- Stanislaw Wozniak
- Angeliki Pantazi
- et al.
- 2017
- ICRC 2017
Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays
- Pritish Narayanan
- Lucas L. Sanches
- et al.
- 2017
- ISCAS 2017
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- VLSI Circuits 2017
Stochastic weight updates in phase-change memory-based synapses and their influence on artificial neural networks
- 2017
- PRIME 2017
Neuromorphic system with phase-change synapses for pattern learning and feature extraction
- Stanislaw Wozniak
- Angeliki Pantazi
- et al.
- 2017
- IJCNN 2017
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response
- S. Sidler
- Irem Boybat
- et al.
- 2016
- ESSDERC 2016
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2014
- A-SSCC 2014