Design of provably correct storage arrays
- R.V. Joshi
- W. Hwang
- et al.
- 2001
- VLSID 2001
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42 results for W. Hwang
`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
High frequency input isolation circuit for asynchronous CMOS macros in PD/SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- IEEE International SOI Conference 2000
Charge transport in the normal state of electron- or hole-doped YBa2Cu3O7-x
- T. Doderer
- C.C. Tsuei
- et al.
- 2000
- Physical Review B - CMMP
`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
Comparison of dual-rail pass transistor logic families in 1.5 V, 0.18 μm CMOS technology for low power applications
- G.D. Gristede
- W. Hwang
- 2000
- GLSVLSI 2000
Scannable pulse-to-static conversion register array for self-timed circuits
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- IEEE International SOI Conference 1999
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
- Wei Hwang
- George Diedrich Gristede
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
Design considerations and implementations of a high performance dynamic register file
- R.V. Joshi
- W. Hwang
- 1999
- VLSID 1999