`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
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42 results for W. Hwang
Comparison of dual-rail pass transistor logic families in 1.5 V, 0.18 μm CMOS technology for low power applications
- G.D. Gristede
- W. Hwang
- 2000
- GLSVLSI 2000
Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- IEEE International SOI Conference 1999
Design considerations and implementations of a high performance dynamic register file
- R.V. Joshi
- W. Hwang
- 1999
- VLSID 1999
660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1998
- IEEE International SOI Conference 1998
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability
- W. Hwang
- G.D. Gristede
- et al.
- 1998
- CICC 1998
Pulse-to-static conversion latch with a self-timed control circuit
- W. Hwang
- R.V. Joshi
- et al.
- 1997
- ICCD 1997
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch
- W.H. Henkels
- W. Hwang
- et al.
- 1997
- VLSI Circuits 1997
Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems
- F.S. Lai
- W. Hwang
- 1993
- VLSI-TSA 1993