low Temperature Silicon Epitaxy by Hot Wall Ultrahigh Vacuum/Low Pressure Chemical Vapor Deposition Techniques: Surface Optimization
- B.S. Meyerson
- E. Ganin
- et al.
- 2019
- JES
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20 results for E. Ganin
Phase edge lithography for sub 0.1 μm electrical channel length in a 200 MM full CMOS process
- P. Agnello
- T. Newman
- et al.
- 1995
- VLSI Technology 1995
A high performance 0.15 μm CMOS
- G. Shahidi
- J. Warnock
- et al.
- 1993
- VLSI Technology 1993
High-Performance Devices for a 0.15-μm CMOS Technology
- G. Shahidi
- James Warnock
- et al.
- 1993
- IEEE Electron Device Letters
Low thermal budget antimony/phosphorus NMOS technology for CMOS
- D.L. Harame
- E. Ganin
- et al.
- 1991
- IEDM 1991
Submicrometer Si and Si-Ge Epitaxial-Bas Double-Poly Self-Aligned Bipolar Transistors
- T.C. Chen
- E. Ganin
- et al.
- 1991
- IEEE T-ED
Epitaxial-base double-poly self-aligned bipolar transistors
- E. Ganin
- T.C. Chen
- et al.
- 1990
- IEDM 1990
As+ and Ga+ implantation and the formation of buried GaAs layers in silicon
- Peter Madakson
- Eti Ganin
- et al.
- 1990
- Journal of Applied Physics
EPI active devices
- G.L. Patton
- B.S. Meyerson
- et al.
- 1990
- Silicon Materials Science and Technology 1990
Shallow p+ junction formation by a reverse-type dopant preamorphization scheme
- E. Ganin
- B. Davari
- et al.
- 1989
- Applied Physics Letters