High performance CMOS variability in the 65nm regime and beyond
- Sani Nassif
- Kerry Bernstein
- et al.
- 2007
- IEDM 2007
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21 results for D.J. Pearson
A 2.3GSample/s 10-tap digital FIR filter for magnetic recording read channels
- S. Rylov
- A. Rylyakov
- et al.
- 2001
- ISSCC 2001
250 MHz digital FIR filters for PRML disk read channels
- D.J. Pearson
- S.K. Reynolds
- et al.
- 1995
- ISSCC 1995
Operational amplifier based test structure for transistor threshold voltage variation
- Brian L. Ji
- Dale J. Pearson
- et al.
- 2008
- ICMTS 2008
High speed test structures for in-line process monitoring and model calibration
- Mark Ketchen
- Manjul Bhushan
- et al.
- 2005
- ICMTS 2005
Technique for rapid, in-line characterization of switching history in partially depleted SOI technologies
- Dale J. Pearson
- Mark B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Low-dropout on-chip voltage regulator for low-power circuits
- Hyun J. Shin
- S.K. Reynolds
- et al.
- 1994
- LPE 1994
Two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM
- D. Moy
- M. Schadt
- et al.
- 1989
- VMIC 1989
Operational amplifier based test structure for quantifying transistor threshold voltage variation
- Brian L. Ji
- Dale J. Pearson
- et al.
- 2009
- IEEE Trans Semicond Manuf