1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
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15 results for Osamu Takahashi
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
The circuits and physical design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- VLSI Circuits 2005
The circuit design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- ICCAD 2005
High-speed, power-conscious circuit design techniques for high-performance computing
- O. Takahashi
- S. Dhong
- et al.
- 2001
- VLSI-TSA 2001
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
690ps read-access latency register file for a GHz integer microprocessor
- O. Takahashi
- Joel Silberman
- et al.
- 1998
- ICCD 1998
1 GHz logic circuits with sense amplifiers
- O. Takahashi
- Naoaki Aoki
- et al.
- 1998
- VLSI Circuits 1998
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- Brian Flachs
- Shigehiro Asano
- et al.
- 2007
- IBM J. Res. Dev
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
- D.C. Pham
- T. Aipperspach
- et al.
- 2006
- IEEE Journal of Solid-State Circuits