Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
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90 results for Meikei Ieong
Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility
- M.M. Frank
- V.K. Paruchuri
- et al.
- 2005
- VLSI-TSA 2005
Ultra-thin SOI replacement gate CMOS with ALD TaN / high-k gate stack
- B. Doris
- B.P. Linder
- et al.
- 2005
- VLSI-TSA 2005
Characteristics of high performance PFETs with embedded SiGe source/drain and 〈100〉 channels on 45° rotated wafers
- Qiqing Ouyang
- Meikei Ieong
- et al.
- 2005
- VLSI Technology 2005
A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/HfO 2)
- S. Zafar
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
On the scalability and carrier transport of advanced CMOS devices
- Meikei Ieong
- Leland Chang
- et al.
- 2005
- ICICDT 2005
Strain for CMOS performance improvement
- Victor Chan
- Ken Rim
- et al.
- 2005
- CICC 2005
Scaling beyond conventional CMOS device
- Meikei Ieong
- Bruce Doris
- et al.
- 2004
- ICSICT 2004
Sub-30 NM abrupt junction formation in strained silicon/silicon-germanium CMOS device
- K.-L. Lee
- F. Cardone
- et al.
- 2004
- ECS Meeting 2004
Fabrication, device design and mobility enhancement of germanium channel MOSFETs
- Huiling Shang
- E. Gousev
- et al.
- 2004
- ICSICT 2004