Die-to-wafer 3D integration technology for high yield and throughput
- Katsuyuki Sakuma
- Paul S. Andry
- et al.
- 2008
- MRS Fall Meeting 2008
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36 results for Chirag S. Patel
Terabus: Chip-to-chip board-level optical data buses
- J.A. Kash
- F.E. Doany
- et al.
- 2008
- LEOS 2008
50μm pitch Pb-free micro-bumps by C4NP technology
- Bing Dang
- Da-Yuan Shih
- et al.
- 2008
- ECTC 2008
300-Gb/s 24-channel bidirectional Si carrier transceiver optochip for board-level interconnects
- Fuad E. Doany
- Clint L. Schow
- et al.
- 2008
- ECTC 2008
3D silicon integration
- J. Knickerbocker
- P. Andry
- et al.
- 2008
- ECTC 2008
Characterization of stacked die using die-to-wafer integration for high yield and throughput
- K. Sakuma
- P. Andry
- et al.
- 2008
- ECTC 2008
300-Gb/s, 24-channel full-duplex, 850-nm, cmos-based optical transceivers
- C.L. Schow
- F.E. Doany
- et al.
- 2008
- OFC/NFOEC 2008
3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections
- Katsuyuki Sakuma
- Paul S. Andry
- et al.
- 2008
- IBM J. Res. Dev
3D chip stacking with C4 technology
- Bing Dang
- Steven L. Wright
- et al.
- 2008
- IBM J. Res. Dev
Three-dimensional silicon integration
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2008
- IBM J. Res. Dev