A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
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8 results for E. Barth
Evaluation of the chemical-mechanical planarization (CMP) performance of silicon nitride and silicon carbide as hard mask materials for Cu-based interconnect technology
- Wei-Tsu Tseng
- Jia Lee
- et al.
- 2002
- MRS Spring Meeting 2002
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric
- R. Filippi
- J.F. McGrath
- et al.
- 2004
- IRPS 2004
Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric
- R. Filippi
- J.F. McGrath
- et al.
- 2004
- IRPS 2004
A high performance 0.13 μm copper BEOL technology with low-k dielectric
- R.D. Goldblatt
- B.N. Agarwala
- et al.
- 2000
- IITC 2000
Integration of copper and fluorosilicate glass for 0.18 μm interconnections
- E. Barth
- T. Ivers
- et al.
- 2000
- IITC 2000
0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999