High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
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6 results for D. Yee
7.9/5.5 psec room/low temperature SOI CMOS
- F. Assaderaghi
- W. Rausch
- et al.
- 1997
- IEDM 1997
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
History dependence of non-fully depleted (NFD) digital SOI circuits
- F. Assaderaghi
- G. Shahidi
- et al.
- 1996
- VLSI Technology 1996
0.25μm low power CMOS devices and circuits from 8 inch SOI materials
- B. Chen
- A.S. Yapsir
- et al.
- 1995
- ICSICT 1995
Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies
- C. Brothers
- R. Pugh
- et al.
- 1997
- IEEE TNS