Conference paper
Within-chip variability analysis
S. Nassif
IEDM 1998
We report a high-performance CMOS operating at 1.5 V with 11.9 ps nominal inverter delay at 0.06/0.08 μm Leff for NMOS and PMOS. Both NMOS and PMOS devices, with 3.6 nm inversion Tox, have the best current drive reported to date at fixed Ioff. Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 9.7 ps inverter delay. These devices are incorporated in a 0.18 μm technology that offers a 4.2 μm2 SRAM cell and dual gate oxide for interfacing to 2.5 V.
S. Nassif
IEDM 1998
A. Deutsch, H. Harrer, et al.
IEDM 1998
E. Burstein
Ferroelectrics
A.B. McLean, R.H. Williams
Journal of Physics C: Solid State Physics