Controlling line-edge roughness and reactive ion etch lag in sub-150 nm features in borophosphosilicate glass
- Parijat Bhatnagar
- Siddhartha Panda
- et al.
- 2007
- Journal of Applied Physics
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4 results for N. Edleman
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Integrated non-SO 2 underlayer and improved line-edge-roughness dielectric etch process using 193 nm bilayer resist
- Parijat Bhatnagar
- Siddhartha Panda
- et al.
- 2006
- Applied Physics Letters
Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow
- D.-G. Park
- Z. Luo
- et al.
- 2004
- VLSI Technology 2004