Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
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3 results for P. Smeys
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
- P. Smeys
- V. McGahay
- et al.
- 2000
- VLSI Technology 2000