A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
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9 results for S.K.H. Fung
Controlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
On the optimal shape and location of silicided source and drain contacts
- P. Oldiges
- C.S. Murthy
- et al.
- 2002
- SISPAD 2002
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- R.V. Joshi
- C.T. Chuang
- et al.
- 2001
- VLSI Technology 2001
Partially depleted silicon-on-insulator (SOI): A device design/modeling and circuit perspective
- F. Assaderaghi
- G. Shahidi
- et al.
- 2000
- ICM 2000
Partially-depleted SOI compact model - formulation and parameter extraction
- S.K.H. Fung
- L. Wagner
- et al.
- 2000
- VLSI Technology 2000
A body-contact SOI MOSFET model for circuit simulation
- P. Su
- S.K.H. Fung
- et al.
- 1999
- IEEE International SOI Conference 1999
PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems