The mechanism of the low-k stress reduction in chip assembly by shorter solder bump height
- Keiji Matsumoto
- Keishi Okamoto
- et al.
- 2017
- InterPACK 2017
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29 results for Keiji Matsumoto
Internet of the Body and Cognitive Hypervisor
- R. Strassle
- S. Gerke
- et al.
- 2017
- CHASE 2017
Thermal performance evaluation of dual-side cooling for a three-dimensional (3D) chip stack: Additional cooling from the laminate (substrate) side
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2016
- ICEP 2016
Advanced interconnect technologies in the era of cognitive computing
- Yasumitsu Orii
- Akihiro Horibe
- et al.
- 2016
- Pan Pacific 2016
Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2014
- 3DIC 2014
Pre-applied inter chip fill for 3D-IC joining
- Yasuhiro Kawase
- Makoto Ikemoto
- et al.
- 2014
- IMAPS 2014
High thermal conductivity underfill for the thermal management of three-dimensional (3D) chip stacks
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2014
- SEMI-THERM 2014
Laminate with thermal - Power insert for efficient front-side heat removal and power delivery
- Dominic Gschwend
- Timo Tick
- et al.
- 2014
- CIPS 2014
Thermo-mechanical evaluation of 3D packages
- Sayuri Kohara
- Akihiro Horibe
- et al.
- 2013
- 3DIC 2013
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack
- Keiji Matsumoto
- Soichiro Ibaraki
- et al.
- 2013
- 3DIC 2013