Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
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25 results for Mark Raymond
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology
- Hiroaki Niimi
- Zuoguang Liu
- et al.
- 2016
- IEEE Electron Device Letters
Ultra low contact resistivities for CMOS beyond 10-nm node
- Zhen Zhang
- Siyuranga Obasa Koswatta
- et al.
- 2013
- IEEE Electron Device Letters
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Validity and Application of the TCR Method to MOL contactS
- E. Milosevic
- Vimal Kamineni
- et al.
- 2018
- IITC 2018
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
- Zuoguang Liu
- Oleg Gluschenkov
- et al.
- 2017
- VLSI Technology 2017
Middle of line RC performance study at the 7 nm node
- Susan Su Chen Fan
- James H.-C. Chen
- et al.
- 2017
- IITC 2017