Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Publications
Date
Featured collections
Popular topics
27 results for Laertis Economikos
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Post cu cmp cleaning of polyurethane pad debris
- Wei-Tsu Tseng
- Elliott Rill
- et al.
- 2013
- ECS J. Solid State Sci. Technol.
Post copper CMP hybrid clean process for advanced BEOL technology
- Wei-Tsu Tseng
- Vamsi Devarapalli
- et al.
- 2013
- IEEE Trans Semicond Manuf
Hybrid clean approach for post-copper CMP defect reduction
- Wei-Tsu Tseng
- Vamsi Devarapalli
- et al.
- 2013
- ASMC 2013
Cu CMP and its challenge for 20nm nodes and beyond
- John H. Zhang
- Wei-Tsu Tseng
- et al.
- 2012
- MRS Spring Meeting 2012
Improvements in profile control using ISPC™ system during the stop-in-oxide CMP step in the RMG process flow on IBM 20nm short-loop wafers
- P. Komarenko
- J. Qian
- et al.
- 2012
- ICPT 2012
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes
- Wei-Tsu Tseng
- Donald Canaperi
- et al.
- 2012
- ASMC 2012
Enabling scatterometry as an in-line measurement technique for 32 nm BEOL application
- M. Golam Faruk
- Shahin Zangooie
- et al.
- 2011
- IEEE Trans Semicond Manuf