Thymesisflow: A software-defined, HW/SW co-designed interconnect stack for rack-scale memory disaggregation
- Christian Pinto
- Dimitris Syrivelis
- et al.
- 2020
- MICRO 2020
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38 results for Peter Hofstee
'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra
- Bedri Sendir
- Madhusudhan Govindaraju
- et al.
- 2018
- CLOUD 2018
Optimized durable commitlog for apache Cassandra using CAPI-flash
- Bedri Sendir
- Madhusudhan Govindaraju
- et al.
- 2016
- CLOUD 2016
The design and implementation of a first-generation CELL Processor
- D.C. Pham
- S. Asano
- et al.
- 2005
- ISSCC 2005
The design and implementation of a first-generation CELL processor
- D.C. Pham
- S. Asano
- et al.
- 2005
- ISSCC 2005
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
Low Latency and High Throughput Write-Ahead Logging Using CAPI-Flash
- Bedri Sendir
- Madhusudhan Govindaraju
- et al.
- 2021
- IEEE TCC
ExtraV: Boosting graph processing near storage with a coherent accelerator
- Jinho Lee
- Heesu Kim
- et al.
- 2017
- VLDB
In-memory database acceleration on FPGAs: a survey
- Jian Fang
- Yvo T. B. Mulder
- et al.
- 2019
- VLDB Journal