Row based dual-vdd island generation and placement
- Hua Xiang
- Haifeng Qian
- et al.
- 2014
- DAC 2014
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31 results for Hua Xiang
History-based VLSI legalization using network flow
- Minsik Cho
- Haoxing Ren
- et al.
- 2010
- DAC 2010
TROY: Track router with yield-driven wire planning
- Minsik Cho
- Hua Xiang
- et al.
- 2007
- DAC 2007
A stochastic approach to handle non-determinism in deep learning-based design rule violation predictions
- Rongjian Liang
- Jiang Hu
- et al.
- 2022
- ICCAD 2022
DRC hotspot prediction at sub-10nm process nodes using customized convolutional network
- Rongjian Liang
- Hua Xiang
- et al.
- 2020
- ISPD 2020
Self-Aligned Double-Patterning Aware Legalization
- Hua Xiang
- Gi Joon Nam
- et al.
- 2020
- DATE 2020
Gate movement for timing improvement on row based Dual-VDD designs
- Hua Xiang
- Lakshmi Reddy
- et al.
- 2016
- ISQED 2016
Depth controlled symmetric function fanin tree restructure
- Hua Xiang
- Lakshmi Reddy
- et al.
- 2013
- ICCAD 2013
LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs
- Minsik Cho
- Hua Xiang
- et al.
- 2013
- ICCAD 2013
Network flow based datapath bit slicing
- Hua Xiang
- Minsik Cho
- et al.
- 2013
- ISPD 2013