Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
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Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2002
- Proceedings of the Custom Integrated Circuits Conference