A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
- Yong Liu
- Ping-Hsuan Hsieh
- et al.
- 2013
- ISSCC 2013
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12 results for Jae-Sun Seo
Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems
- Min-Kyu Song
- Ji-Hoon Kang
- et al.
- 2023
- ACS Nano
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering
- Suyoung Bang
- Jae-Sun Seo
- et al.
- 2016
- IEEE JSSC
Crosstalk-aware PWM-based on-chip links with self-calibration in 65 nm CMOS
- Jae-Sun Seo
- David Blaauw
- et al.
- 2011
- IEEE JSSC
Digital-Assisted Analog In-Memory Computing with RRAM Devices
- Zhenyu Wang
- Pragnya Sudershan Nalla
- et al.
- 2023
- VLSI-TSA 2023
IMC Architecture for Robust DNN Acceleration
- Gokul Krishnan
- Zhenyu Wang
- et al.
- 2022
- ICSICT 2022
A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple
- Suyoung Bang
- Jae-Sun Seo
- et al.
- 2015
- VLSI Circuits 2015
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
- Jae-Sun Seo
- Bernard Brezzo
- et al.
- 2011
- CICC 2011
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference
- Arnab Neelim Mazumder
- Jian Meng
- et al.
- 2021
- IEEE JESTCS
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration
- Gokul Krishnan
- Zhenyu Wang
- et al.
- 2022
- IEEE TCADIS