Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization
- N. Gong
- Malte J. Rasch
- et al.
- 2022
- IEDM 2022
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14 results for Jeffrey Shearer
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Characterization of TSV etch from a sustainability standpoint
- Osakpolo Isowamwen
- Nathan Marchack
- et al.
- 2023
- SPIE Advanced Lithography 2023
Particle reduction in back end of line plasma-etching process: CFM: Contamination free manufacturing
- Lijuan Zou
- Alex Vaghese
- et al.
- 2018
- ASMC 2018
Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning
- Angelique Raley
- Joe Lee
- et al.
- 2018
- SPIE Advanced Lithography 2018
Defect detection strategies and process partitioning for SE EUV patterning
- Luciana Meli
- Karen Petrillo
- et al.
- 2018
- SPIE Advanced Lithography 2018
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
An OCD perspective of line edge and line width roughness metrology
- Ravi Bonam
- R. Muthinti
- et al.
- 2017
- SPIE Advanced Lithography 2017
Single-expose patterning development for EUV lithography
- Anuja De Silva
- Karen Petrillo
- et al.
- 2017
- SPIE Advanced Lithography 2017