Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
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62 results for Dechao Guo
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- R. Bao
- C. Durfee
- et al.
- 2021
- IEDM 2021
Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies
- M. Bhuiyan
- M. Kim
- et al.
- 2021
- IEDM 2021
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel
- Shogo Mochizuki
- M. Bhuiyan
- et al.
- 2020
- IEDM 2020