A novel integration scheme for self-aligend Ru topvia as post-Cu alternative metal interconnectsK. MotoyamaD. Metzleret al.2023IITC/MAM 2023
Methodology Development to Benchmark Power Delivery Designs in Advanced Technology NodesNicholas A. LanzilloA. Chuet al.2023SPIE Advanced Lithography + Patterning 2023
Capacitive Impacts of Etch-Induced Dielectric Damage in Highly-Scaled Interconnect ArchitecturesJanet M. WilsonNicholas A. Lanzillo2022IITC 2022
Metal-induced line width variability challenge and mitigation strategy in advanced post-Cu interconnectsKoichi MotoyamaNicholas A. Lanzilloet al.2022IITC 2022
Dual Damascene BEOL Extendibility With Cu Reflow / Selective TaN And Co/Cu CompositeP. BhosaleN. Lanzilloet al.2021VLSI Technology 2021
Comprehensive BEOL Performance Assessment: Interconnects Optimized for Signal Routing and Power Delivery in Advanced CMOS Technology Nodes (Invited)Nicholas A. LanzilloRwik Senguptaet al.2020IITC 2020
Composite Interconnects for High-Performance Computing beyond the 7nm NodeP. BhosaleS. Parikhet al.2020VLSI Technology 2020
A Materials Screening Methodology for Scaled Non-Volatile Memory in the AI EraNicholas A. LanzilloR. R. Robison2019ANTS 2019
Technology challenges and enablers to extend Cu metallization to beyond 7 nm nodeTakeshi NogamiH. Huanget al.2019VLSI Technology 2019
Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyondNicholas A. LanzilloKoichi Motoyamaet al.2018IITC 2018