Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
Publications
Date
Featured collections
Popular topics
31 results for D.L. Rath
Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
- Benjamin D. Briggs
- C.B. Peethala
- et al.
- 2017
- IEDM 2017
Resistance contributions to copper interconnects
- C. Witt
- F. Baumann
- et al.
- 2017
- IITC 2017
Copper-to-dielectric heterogeneous bonding for 3D integration
- Wei Lin
- Juntao Li
- et al.
- 2014
- LTB-3D 2014
CVD-Co/Cu(Mn) integration and reliability for 10 nm node
- Takeshi Nogami
- M. He
- et al.
- 2013
- IITC 2013
TiN metal hard mask removal with selectivity to tungsten and TiN liner
- S. Lippy
- L. Chen
- et al.
- 2013
- ECS Transactions
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
CoWP metal caps for reliable 32 nm 1X Cu interconnects in porous ULK (k=2.4)
- E. Huang
- M. Oh
- et al.
- 2009
- ADMETA 2009
A multilevel copper/low-k/airgap BEOL technology
- S.V. Nitta
- S. Ponoth
- et al.
- 2007
- ADMETA 2007
Etching of copper in deionized water rinse
- J.P. Gambino
- J. Robbins
- et al.
- 2008
- IPFA 2008