Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
- Benjamin D. Briggs
- C.B. Peethala
- et al.
- 2017
- IEDM 2017
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31 results for D.L. Rath
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Successful dual damascene integration of extreme low k materials (k < 2.0) using a novel gap fill based integration scheme
- S.V. Nitta
- S. Purushothaman
- et al.
- 2004
- IEDM 2004
Studies of the relationship between megasonics, surface etching, and particle removal in SC-1 solutions
- S.L. Cohen
- D.L. Rath
- et al.
- 1995
- MRS Spring Meeting 1995
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
Resistance contributions to copper interconnects
- C. Witt
- F. Baumann
- et al.
- 2017
- IITC 2017
Copper-to-dielectric heterogeneous bonding for 3D integration
- Wei Lin
- Juntao Li
- et al.
- 2014
- LTB-3D 2014
CVD-Co/Cu(Mn) integration and reliability for 10 nm node
- Takeshi Nogami
- M. He
- et al.
- 2013
- IITC 2013
TiN metal hard mask removal with selectivity to tungsten and TiN liner
- S. Lippy
- L. Chen
- et al.
- 2013
- ECS Transactions
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012