Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model
- Sujit K. Singh
- Sumreti Gupta
- et al.
- 2022
- IEEE Electron Device Letters
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21 results for Abhisek Dixit
Evaluation of 10-nm Bulk FinFET RF Performance - Conventional Versus NC-FinFET
- R. Singh
- K. Aditya
- et al.
- 2018
- IEEE Electron Device Letters
Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS
- Chandan Kumar Jha
- Charu Gupta
- et al.
- 2020
- EDTM 2020
Impact of Hot Carrier Stress on RF FOMs in 10-nm Bulk N-Channel FinFETs
- Anshul Gupta
- Charu Gupta
- et al.
- 2019
- IIRW 2019
Comparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET
- Ishita Jain
- Anshul Gupta
- et al.
- 2016
- ICEE 2016
7-nm Nanowire FET process variation modeling using industry standard BSIM-CMG model
- R. Singh
- K. Aditya
- et al.
- 2016
- ICEE 2016
Nanowire FET design for 7-nm SOI-CMOS technology
- Ishita Jain
- Anil K. Bansal
- et al.
- 2015
- S3S 2015
Characterization of silicide-silicon interface contact resistivity using 1-D dual transmission line model approximation of modified cross bridge kelvin measurements
- Ankur Arya
- Balaji Jayaraman
- et al.
- 2011
- IWPSD 2011
Measurement and analysis of source/drain contact resistance in FinFETs
- Abhisek Dixit
- Nadine Collaert
- et al.
- 2011
- IWPSD 2011
Comparison of LER induced mismatch in NWFET and NSFET for 5-nm CMOS
- Chandan Kumar Jha
- Pritam Yogi
- et al.
- 2020
- IEEE J-EDS