Minimizing inductive noise in system-on-a-chip with multiple power gating structures
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2003
- ESSCIRC 2003
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43 results for Kevin G. Stawiasz
Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
- D. Heidel
- S. Dhong
- et al.
- 1998
- VTS 1998
Low cost 10 gigabit/s optical interconnects for parallel processing
- D. Kuchta
- J.D. Crow
- et al.
- 1998
- MPPOI 1998
3.3 V 20-channel 500 Mb/s/ch optical receiver with integrated optical detectors in 1.2 mm GaAs
- J. Yang
- Joong-ho Choi
- et al.
- 1998
- ISSCC 1998
A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology
- Jungwook Yang
- Joongho Choi
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
Automated testing methodologies for low cost, parallel optical bus components
- K. Stawiasz
- D. Kuchta
- et al.
- 1997
- ECTC 1997
500 Mb/s, 20-channel CMOS laser diode array driver for a parallel optical bus
- Peter Xiao
- D. Kuchta
- et al.
- 1997
- ISSCC 1997
500 MS/s 10-bit CMOS D/A converter
- Peter Xiao
- John Shin
- et al.
- 1996
- ASICON 1996
Jitney parallel optical interconnect
- J.D. Crow
- Joong-ho Choi
- et al.
- 1996
- ECTC 1996