Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
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14 results for Todd Bailey
Lithographic qualification of high-Transmission mask blank for 10nm node and beyond
- Yongan Xu
- Tom Faure
- et al.
- 2016
- SPIE Advanced Lithography 2016
Methodology for determining CD-SEM measurement condition of sub-20nm resist patterns for 0.33NA EUV lithography
- Nobuhiro Okai
- Erin Lavigne
- et al.
- 2015
- SPIE Advanced Lithography 2015
Scatterometry-based defect detection for DSA in-line process control
- Robin Chao
- Chi Chun Liu
- et al.
- 2015
- SPIE Advanced Lithography 2015
Machine learning and predictive data analytics enabling metrology and process control in IC fabrication
- Narender Rana
- Yunlin Zhang
- et al.
- 2015
- SPIE Advanced Lithography 2015
Leveraging data analytics, patterning simulations and metrology models to enhance CD metrology accuracy for advanced IC nodes
- Narender Rana
- Yunlin Zhang
- et al.
- 2014
- SPIE Advanced Lithography 2014
Novel in-line metrology methods for Fin pitch walking monitoring in 14nm node and beyond
- Robin Chao
- Kriti Kohli
- et al.
- 2014
- SPIE Advanced Lithography 2014
Precise CD-SEM metrology of resist patterns at around 20 nm for 0.33NA EUV lithography
- Nobuhiro Okai
- Erin Lavigne
- et al.
- 2014
- SPIE Advanced Lithography 2014
A SiCOH BEOL interconnect technology for high density and high performance 65 nm CMOS applications
- Matthew Angyal
- Jason Gill
- et al.
- 2005
- AMC 2005
First microprocessors with immersion lithography
- D. Gil
- T. Bailey
- et al.
- 2005
- SPIE Advanced Lithography 2005