A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2014
- A-SSCC 2014
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53 results for Martin L. Schmatz
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation
- Martin L. Schmatz
- Rik Jongerius
- et al.
- 2014
- ICASSP 2014
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- VLSI Circuits 2013
5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS
- George Von Bueren
- Lucio Rodoni
- et al.
- 2008
- ESSCIRC 2008
A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI
- Thomas Toifl
- Christian Menolfi
- et al.
- 2008
- A-SSCC 2008
Integration of optical I/O with organic chip packages
- Bert J. Offrein
- Christoph Bergen
- et al.
- 2008
- SPIE Photonics Europe 2008
Integration of optical I/O with organic chip packages
- Christoph Berger
- Laurent Dellmann
- et al.
- 2008
- SPIE IOPTO 2008
A low-power 40 Gbit/s receiver circuit based on full-swing CMOS-style clocking
- Thomas Toifl
- Christian Menolfi
- et al.
- 2007
- CSICS 2007
Low-cost electro-optical package for use with PCB-embedded waveguides
- Jonas Weiss
- Christoph Berger
- et al.
- 2007
- Optics East 2007
A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential Gain in 90-nm CMOS
- Jonas R. M. Weiss
- Martin L. Schmatz
- et al.
- 2006
- RFIC 2006