Danny Luu, Lukas Kull, et al.
IEEE JSSC
A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of - 16 dB up to 10 GHz a 40 μ m,×, 40 μ m T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 μm ×, {360}\ μm. In addition to the transmitter design, guidelines for the T-coil design are presented. © 2006 IEEE.
Danny Luu, Lukas Kull, et al.
IEEE JSSC
Lukas Kull, Danny Luu, et al.
CSICS 2016
Andreea Anghel, Rik Jongerius, et al.
ICASSP 2014
Roger Dangel, Folkert Horst, et al.
IPC 2014