A 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
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25 results for Yong Liu
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI
- Mihai Sanduleanu
- Alberto Valdes-Garcia
- et al.
- 2013
- CICC 2013
Solid-state and biological systems interface
- Nan Sun
- Yong Liu
- et al.
- 2012
- ESSCIRC 2012
Solid-State and biological systems interface
- Nan Sun
- Yong Liu
- et al.
- 2012
- ESSDERC 2012
Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts
- Xiaoxiong Gu
- Joel Silberman
- et al.
- 2012
- EPEPS 2012
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
- Jae-Sun Seo
- Bernard Brezzo
- et al.
- 2011
- CICC 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011
Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology
- Xiaoxiong Gu
- Joel A. Silberman
- et al.
- 2013
- IEEE Transactions on CPMT
Small NMR biomolecular sensors
- Nan Sun
- Yong Liu
- et al.
- 2013
- Solid-State Electronics