A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- Sergey V. Rylov
- Troy Beukema
- et al.
- 2016
- ISSCC 2016
Publications
Date
Featured collections
Popular topics
25 results for Yong Liu
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
- Yong Liu
- Ping-Hsuan Hsieh
- et al.
- 2013
- ISSCC 2013
2.5D and 3D technology challenges and test vehicle demonstrations
- John Knickerbocker
- Paul Andry
- et al.
- 2012
- ECTC 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
- Ankur Agrawal
- John Bulzacchelli
- et al.
- 2012
- ISSCC 2012
A compact low-power 3D I/O in 45nm CMOS
- Yong Liu
- Wing Luk
- et al.
- 2012
- ISSCC 2012
3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections
- Joana Maria
- Bing Dang
- et al.
- 2011
- ECTC 2011
Electrical characterization of 3D Through-Silicon-Vias
- Fei Liu
- Xiaoxiong Gu
- et al.
- 2010
- ECTC 2010
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
- Yong Liu
- Byungsub Kim
- et al.
- 2009
- ISSCC 2009
A 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC