Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
- Subhendu Roy
- Mihir Choudhury
- et al.
- 2016
- IEEE TCADIS
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27 results for David Z. Pan
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
- Subhendu Roy
- Mihir Choudhury
- et al.
- 2014
- IEEE TCADIS
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
- Subhendu Roy
- Mihir Choudhury
- et al.
- 2013
- DAC 2013
Chemical-mechanical polishing aware application-specific 3D NoC design
- Wooyoung Jang
- Ou He
- et al.
- 2011
- ICCAD 2011
Novel binary linear programming for high performance clock mesh synthesis
- Minsik Cho
- David Z. Pan
- et al.
- 2010
- ICCAD 2010
CAD for double patterning lithography
- David Z. Pan
- Jae-Seok Yang
- et al.
- 2010
- ICICDT 2010
Manufacturability aware routing in nanometer VLSI
- David Z. Pan
- Minsik Cho
- et al.
- 2010
- Foundations and Trends in Electronic Design Automation
Layout optimizations for double patterning lithography
- David Z. Pan
- Jae-Seok Yang
- et al.
- 2009
- ASICON 2009
ELIAD: Efficient Lithography Aware Detailed routing algorithm with compact and macro post-OPC printability prediction
- Minsik Cho
- Kun Yuan
- et al.
- 2009
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ELIAD: Efficient lithography aware detailed routing algorithm with compact and macro post-OPC printability prediction
- Minsik Cho
- Kun Yuan
- et al.
- 2009
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems