High Performance Nanosheet Technology Optimized for 77 K
- R. Bao
- L. Qin
- et al.
- 2023
- IEDM 2023
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14 results for Carl Radens
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Embedded memory considerations in SOI
- G. Wang
- Carl Radens
- et al.
- 2010
- IEEE International SOI Conference 2010
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
Characterization of Across-device Linewidth Variation (ADLV) for 65 nm logic SRAM using CDSEM and linewidth roughness algorithms
- W. Chu
- C. Radens
- et al.
- 2006
- SPIE Advanced Lithography 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
- C. Radens
- U. Gruening
- et al.
- 1998
- VLSI Technology 1998
A universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM
- Rajiv V. Joshi
- Sudesh Saroop
- et al.
- 2016
- IEEE Transactions on VLSI Systems