A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
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27 results for Jente B. Kuang
Circuit techniques utilizing independent gate control in double-gate technologies
- Jente B. Kuang
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on VLSI Systems
Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation
- Rouwaida Kanj
- Rajiv V. Joshi
- et al.
- 2008
- IEEE Trans Semicond Manuf
Low-power high-performance asymmetrical double-gate circuits using back-gate-controlled wide-tunable-range diode voltage
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2007
- IEEE Transactions on Electron Devices
Restoration of Controllable Hysteresis in Partially Depleted SOI CMOS Schmitt Trigger Circuits
- Jente B. Kuang
- Ching-Te Chuang
- 2004
- IEEE TCAS-II
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology
- Jente B. Kuang
- David H. Allen
- et al.
- 2001
- IEEE Journal of Solid-State Circuits
Floating-body effects in partially depleted SOI CMOS circuits
- Pong-Fei Lu
- Ching-Te Chuang
- et al.
- 1997
- IEEE Journal of Solid-State Circuits