TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
- Filipp Akopyan
- Jun Sawada
- et al.
- 2015
- IEEE TCADIS
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27 results for Jente B. Kuang
Variability aware simulation based design-technology cooptimization (DTCO) Flow in 14 nm FinFET/SRAM cooptimization
- Asen Asenov
- Binjie Cheng
- et al.
- 2015
- IEEE T-ED
Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators
- Jente B. Kuang
- Keith A. Jenkins
- et al.
- 2013
- ESSCIRC 2013
SRAM device and cell co-design considerations in a 14nm SOI FinFET technology
- Binjie Cheng
- Xingsheng Wang
- et al.
- 2013
- ISCAS 2013
The design and characterization of a half-volt 32 nm dual-read 6T SRAM
- Jente B. Kuang
- Jeremy D. Schaub
- et al.
- 2011
- IEEE TCAS-I
A 32nm 0.5V-supply dual-read 6T SRAM
- Jente B. Kuang
- J. Schaub
- et al.
- 2010
- CICC 2010
TCAD/physics-based analysis of high-density dual-BOX FD/SOI SRAM cell with improved stability
- Keunwoo Kim
- Jente B. Kuang
- et al.
- 2009
- IEEE Transactions on Electron Devices
Statistical yield analysis of silicon-on-insulator embedded DRAM
- R. Kanj
- R.V. Joshi
- et al.
- 2009
- ISQED 2009
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- J.B. Kuang
- A. Mathews
- et al.
- 2008
- ESSCIRC 2008