Optimal dual-VT design in sub-100 nanometer PDSOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- VLSID 2008
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79 results for Keunwoo Kim
Optimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Device design and optimization methodology for leakage and variability reduction in sub-45-nm FD/SOI SRAM
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Design and analysis of thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- ISLPED 2007
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2007
- ISLPED 2007
A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2007
- VLSID 2007
Leakage analysis for FinFET devices using self-consistent electro-thermal modeling
- Satish Kumar
- Rajiv V. Joshi
- et al.
- 2007
- ICICDT 2007
High-performance device optimization and dual-VT technology options for doublegate FET
- Aditya Bansal
- Keunwoo Kim
- et al.
- 2007
- ICICDT 2007
Phonon Boltzmann transport based electro-thermal analysis of nano-scale asymmetrical double-gate finfet device
- Chunjian Ni
- Rajiv V. Joshi
- et al.
- 2007
- ASME Electronic and Photonics Packaging Division 2007
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
- Ching-Te Chuang
- Saibal Mukhopadhyay
- et al.
- 2007
- MTDT 2007