High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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26 results for B. Jagannathan
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
Noise performance of a low base resistance 200 GHz SiGe technology
- D.R. Greenberg
- B. Jagannathan
- et al.
- 2002
- IEDM 2002
3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2003
- IEEE Electron Device Letters
A 4.2-ps ECL ring-oscillator in a 285-GHz f MAX SiGe technology
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2002
- IEEE Electron Device Letters
Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology
- B. Jagannathan
- M. Khater
- et al.
- 2002
- IEEE Electron Device Letters
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
Leakage engineering enabling PDSOI ring oscillators operating in sub-100pA/μm Ioff regime
- Zhibin Ren
- Jin Cai
- et al.
- 2011
- CSTIC 2011
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- A. Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- VLSI-TSA 2010