Formal Techniques for Effective Co-verification of Hardware/Software Co-designs
- Rajdeep Mukherjee
- Mitra Purandare
- et al.
- 2017
- DAC 2017
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20 results for Raphael Polig
Acceleration-As-A-μService: A Cloud-native Monte-Carlo Option Pricing Engine on CPUs, GPUs and Disaggregated FPGAs
- 2021
- CLOUD 2021
Accelerated analysis of Boolean gene regulatory networks
- Mitra Purandare
- Raphael Polig
- et al.
- 2017
- FPL 2017
Network-attached FPGAs for data center applications
- Jagath Weerasinghe
- Raphael Polig
- et al.
- 2016
- FPT 2016
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA
- Heiner Giefers
- Peter Staar
- et al.
- 2016
- FPL 2016
Annotation-based finite-state transducers on reconfigurable devices
- Raphael Polig
- Kubilay Atasu
- et al.
- 2016
- FPL 2016
A soft-core processor array for relational operators
- Raphael Polig
- Heiner Giefers
- et al.
- 2015
- ASAP 2015
Accelerating arithmetic kernels with coherent attached FPGA coprocessors
- Heiner Giefers
- Raphael Polig
- et al.
- 2015
- DATE 2015
Compiling text analytics queries to FPGAs
- Raphael Polig
- Kubilay Atasu
- et al.
- 2014
- FPL 2014
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system
- Heiner Giefers
- Raphael Polig
- et al.
- 2014
- ASAP 2014