RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference
- Swagath Venkataramani
- Vijayalakshmi Srinivasan
- et al.
- 2021
- ISCA 2021
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28 results for Joel Silberman
'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling
- Ankur Agrawal
- Saekyu Lee
- et al.
- 2021
- ISSCC 2021
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias
- Matt Wordeman
- Joel Silberman
- et al.
- 2012
- ISSCC 2012
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- Sae Kyu Lee
- Ankur Agrawal
- et al.
- 2021
- IEEE JSSC
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
- Jinwook Oh
- Sae Kyu Lee
- et al.
- 2020
- VLSI Circuits 2020
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference
- Bruce Fleischer
- Sunil Shukla
- et al.
- 2018
- VLSI Circuits 2018
Thermal analysis of multi-layer functional 3D logic stacks
- Michael Scheuermann
- Shurong Tian
- et al.
- 2016
- 3DIC 2016
3D integration ESD protection design and analysis
- Souvick Mitra
- Ephrem Gebreselasie
- et al.
- 2015
- EOS/ESD 2015