Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- S. Lee
- et al.
- 2013
- CICC 2013
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9 results for Scott K. Springer
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
Elements of statistical SPICE models
- Ning Lu
- Josef Watts
- et al.
- 2009
- NSTI-Nanotech 2009
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
SOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007
Experimental study of gate-first finfet threshold-voltage mismatch
- Qintao Zhang
- Cindy Wang
- et al.
- 2014
- IEEE T-ED
Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- Sungjae Lee
- et al.
- 2014
- IEEE TCAS-I
Modeling of variation in submicrometer CMOS ULSI technologies
- Scott K. Springer
- Sungjae Lee
- et al.
- 2006
- IEEE Transactions on Electron Devices