S. Narasimha, P. Chang, et al.
IEDM 2012
We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging device modeling features and their enhancements. At nominal L poly, floating-body NFET and PFET demonstrate peak f T of 300GHz and fMAX of higher than 350GHz with excellent model-to-hardware accuracy. For precision analog circuit design, body-contacted (BC) FETs and various passives are offered, and their performance and modeling accuracy are co-optimized to push the technology limit and achieve state-of-the-art circuits, e.g., 28Gb/s serial link transceiver and LC-tank VCO operating at higher than 100GHz. © 2012 IEEE.
S. Narasimha, P. Chang, et al.
IEDM 2012
Ruqiang Bao, Brian Greene, et al.
IEDM 2015
Daeik Kim, Jonghae Kim, et al.
IEEE Electron Device Letters
X. Yu, Oleg Gluschenkov, et al.
IEDM 2011