Bonding technologies for chip level and wafer level 3D integration
- Katsuyuki Sakuma
- Spyridon Skordas
- et al.
- 2014
- ECTC 2014
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5 results for Luc Guerin
Three-dimensional chip stack with integrated decoupling capacitors and thru-si via interconnects
- Bing Dang
- Michael Shapiro
- et al.
- 2010
- IEEE Electron Device Letters
Reliable through silicon vias for 3D silicon applications
- M.J. Shapiro
- M. Interrante
- et al.
- 2009
- IITC 2009
C4NP technology: Present and future
- Eric Perfecto
- Da-Yuan Shih
- et al.
- 2008
- GBC 2008
Chip-to-Package Interaction for a 90 nm Cu / PECVD Low-k technology
- W. Landers
- D. Edelstein
- et al.
- 2004
- IITC 2004