Conference paper
Transferrable fine pitch probe technology
Y. Liu, S.L. Wright, et al.
ECTC 2014
In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nFmm2 is achieved with two-layer Si interposer chip stacks. © 2006 IEEE.
Y. Liu, S.L. Wright, et al.
ECTC 2014
Bing Dang, Bucknell Webb, et al.
ECTC 2014
Bing Dang, Steven Wright, et al.
ECTC 2013
Xiaoxiong Gu, Joel A. Silberman, et al.
IEEE Transactions on CPMT