Bing Dang, Muhannad S. Bakir, et al.
IEEE Transactions on Advanced Packaging
In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nFmm2 is achieved with two-layer Si interposer chip stacks. © 2006 IEEE.
Bing Dang, Muhannad S. Bakir, et al.
IEEE Transactions on Advanced Packaging
Bucknell Webb, Paul Andry
ECTC 2015
Paul Andry, Bing Dang, et al.
ECTC 2011
John Knickerbocker, Paul Andry, et al.
ECTC 2012