Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
- Ram Krishna
- Atom O. Watanabe
- et al.
- 2023
- ECTC 2023
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11 results for Elyse Rosenbaum
Semantic Autoencoder for Modeling BEOL and MOL Dielectric Lifetime Distributions
- Weiman Yan
- Ernest Wu
- et al.
- 2023
- IRPS 2023
A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network
- Ram Krishna
- Thong Nguyen
- et al.
- 2022
- EDAPS 2022
ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology
- James Di Sarro
- Yang Yang
- et al.
- 2009
- EOS/ESD 2009
Evaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2007
- IRPS 2007
Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65NM bulk CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2006
- IRPS 2006
Double-gate FET technology for RF applications: Device characteristics and low noise amplifier design
- Karan Bhatia
- Keunwoo Kim
- et al.
- 2006
- IEEE SOI 2006
A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection
- Junjun Li
- Robert Gauthier
- et al.
- 2004
- EOS/ESD 2004
Electrostatic discharge characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors
- S. Voldman
- P. Juliano
- et al.
- 2000
- EOS/ESD 2000
Critical evaluation of SOI design guidelines
- Rouwaida Kanj
- Elyse Rosenbaum
- 2004
- IEEE Transactions on VLSI Systems