Embedding read-only memory in spin-transfer torque MRAM-based on-chip caches
- Xuanyao Fong
- Rangharajan Venkatesan
- et al.
- 2016
- IEEE Transactions on VLSI Systems
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45 results for Kaushik Roy
Energy-delay optimization of the STT MRAM write operation under process variations
- Dongsoo Lee
- Kaushik Roy
- 2014
- IEEE TNANO
Thermoelectric spin-transfer torque MRAM with fast bidirectional writing using magnonic current
- Niladri N. Mojumder
- Kaushik Roy
- et al.
- 2013
- IEEE Transactions on Magnetics
Magnonic spin-transfer torque MRAM with low power, high speed, and error-free switching
- Niladri N. Mojumder
- David W. Abraham
- et al.
- 2012
- IEEE Transactions on Magnetics
Column-selection-enabled 8T SRAM array with 1R/1W multi-port operation for DVFS-enabled processors
- Sang Phill Park
- Soo Youn Kim
- et al.
- 2011
- ISLPED 2011
Robust level converter for sub-threshold/super-threshold operation:100 mV to 2.5 v
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2011
- IEEE Transactions on VLSI Systems
Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor
- Mesut Meterelliyoz
- Peilin Song
- et al.
- 2010
- IEEE TCAS-I
Self-repairing SRAM using on-chip detection and compensation
- Niladri Narayan Mojumder
- Saibal Mukhopadhyay
- et al.
- 2010
- IEEE Transactions on VLSI Systems
Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM
- Ashish Goel
- Sumeet Gupta
- et al.
- 2009
- DRC 2009
A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2009
- IEEE Journal of Solid-State Circuits