First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications
- H. Wu
- V. Katragadda
- et al.
- 2021
- IEDM 2021
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56 results for M. Wordeman
A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
One-Micron Polycide (WSI2 on Poly-Si) MOSFET Technology
- M.Y. Tsai
- H.H. Chao
- et al.
- 2019
- JES
Analytical test of 3D integrated circuits
- Raphael P. Robertazzi
- Micheal Scheurman
- et al.
- 2017
- ITC 2017
Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks
- Pascale Gagnon
- Christian Bergeron
- et al.
- 2017
- ECTC 2017
Thermal analysis of multi-layer functional 3D logic stacks
- Michael Scheuermann
- Shurong Tian
- et al.
- 2016
- 3DIC 2016
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- Toshiaki Kirihata
- John Golz
- et al.
- 2016
- IEEE JESTCS
A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias
- Matt Wordeman
- Joel Silberman
- et al.
- 2012
- ISSCC 2012
Process-design considerations for three dimensional memory integration
- S.S. Iyer
- T. Kirihata
- et al.
- 2009
- VLSI Technology 2009