Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- Toshiaki Kirihata
- John Golz
- et al.
- 2016
- IEEE JESTCS
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56 results for M. Wordeman
Wafer-level 3D integration technology
- Steven J. Koester
- Albert M. Young
- et al.
- 2008
- IBM J. Res. Dev
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- Toshiaki Kirihata
- Martin Gall
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
Flexible test mode approach for 256-Mb DRAM
- Toshiaki Kirihata
- Hing Wong
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Fault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEEE Journal of Solid-State Circuits
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ
- Yohji Watanabe
- Hing Wong
- et al.
- 1996
- IEICE Transactions on Electronics
Fault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEICE Transactions on Electronics
A Comprehensive Study of Hot-Carrier Instability in P- and N-Type Poly-SI Gated MOSFET’s
- Charles C.-H. Hsu
- Duen-Shun Wen
- et al.
- 1994
- IEEE Transactions on Electron Devices