Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
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64 results for J. Demarest
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
Experimental study of PVD Cu/CVD Co bilayer dissolution for BEOL Cu interconnect applications
- X. Sun
- B. Peethala
- et al.
- 2017
- ECS Meeting 2017
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
- Zuoguang Liu
- Oleg Gluschenkov
- et al.
- 2017
- VLSI Technology 2017
Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node
- Takeshi Nogami
- X. Zhang
- et al.
- 2017
- VLSI Technology 2017
Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines
- Takeshi Nogami
- Raghuveer Patlolla
- et al.
- 2017
- IITC 2017
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Advanced in-line metrology strategy for self-aligned quadruple patterning
- Robin Chao
- Mary Breton
- et al.
- 2016
- SPIE Advanced Lithography 2016
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
Copper-to-dielectric heterogeneous bonding for 3D integration
- Wei Lin
- Juntao Li
- et al.
- 2014
- LTB-3D 2014