A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
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29 results for O. Van Der Straten
First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications
- H. Wu
- V. Katragadda
- et al.
- 2021
- IEDM 2021
Material to system-level benchmarking of CMOS-integrated RRAM with ultra-fast switching for low power on-chip learning
- Minhaz Abedin
- Nanbo Gong
- et al.
- 2023
- Scientific Reports
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters
Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects
- Nicholas A. Lanzillo
- Kisik Choi
- et al.
- 2019
- IEEE Electron Device Letters
Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and beyond
- Koichi Motoyama
- O. Van Der Straten
- et al.
- 2018
- IITC 2018
Experimental study of PVD Cu/CVD Co bilayer dissolution for BEOL Cu interconnect applications
- X. Sun
- B. Peethala
- et al.
- 2017
- ECS Meeting 2017
BEOL process integration for the 7 nm technology node
- T. Standaert
- Genevieve Beique
- et al.
- 2016
- IITC/AMC 2016
ALD and PVD tantalum nitride barrier resistivity and their significance in via resistance trends
- O. Van Der Straten
- X. Zhang
- et al.
- 2014
- ECSSMEQ 2014
Electrical properties and reliability of ALD TaN barrier for sub-90nmPitch Cu interconnects
- Tibor Bolom
- J. Lee
- et al.
- 2013
- ADMETA 2013