Asymmetrical SRAM cells with enhanced read and write margins
- Keunwoo Kim
- Jae-Joon Kim
- et al.
- 2007
- VLSI-TSA 2007
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51 results for Ching-Te Chuang
Device footprint scaling for ultra thin body fully depleted SOI
- Jie Deng
- Keunwoo Kim
- et al.
- 2007
- ISQED 2007
Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability
- Jae-Joon Kim
- Keunwoo Kim
- et al.
- 2006
- ESSCIRC 2006
Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability
- Jae-Joon Kim
- Keunwoo Kim
- et al.
- 2006
- ESSDERC 2006
High performance MTCMOS technique for leakage reduction in hybrid SOI-epitaxial technologies with enhanced-mobility PFET header
- Koushik K. Das
- Shih-Hsien Lo
- et al.
- 2006
- VLSID/Embedded 2006
Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2005
- ISQED 2005
Back-gate controlled READ SRAM with improved stability
- Jae-Joon Kim
- Keunwoo Kim
- et al.
- 2005
- IEEE International SOI Conference 2005
Single polysilicon gate high-density logic using independently-controlled double-gate devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- A-SSCC 2005
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2005
- ISLPED 2005
Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2004
- ISLPED 2004